The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device having an MIM (Metal-Insulation-Metal) capacitor and a method for fabricating the semiconductor device.
Capacitor elements are important members of LSI, etc. having analog circuits.
Conventionally the capacitor elements have used polysilicon layer, impurity diffused layers, etc. as the electrodes, but recently capacitor elements called MIM capacitors are noted.
An MIM capacitor is a capacitor comprising a capacitor insulation film between a pair of electrodes of a metal. MIM capacitors can improve capacitor precision and frequency characteristics, and are much noted.
However, the above-described MIM capacitors are all vulnerable to external noises. Techniques for making the MIM capacitors invulnerable to external noises have been required.
An object of the present invention is to provide a semiconductor device which can prevent noises from combining with the MIM capacitor, and a method for fabricating the semiconductor device.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a capacitor element formed above the semiconductor substrate and including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film; a shield layer formed at least either of above and below the capacitor element; and a lead-out interconnection layer formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes being formed in each of the shield layer and the lead-out interconnection layer.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a capacitor element formed above the semiconductor substrate and including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film; a lower shield layer formed below the capacitor element; an upper shield layer formed above the capacitor element; a lower electrode lead-out interconnection layer formed between the capacitor element and the lower shield layer and electrically connected to the lower electrode; and an upper electrode lead-out interconnection layer formed between the capacitor element and the upper shield layer and electrically connected to the upper electrode, a plurality of holes being formed in each of the lower shield layer, the upper shield layer, the lower electrode lead-out interconnection layer and the upper electrode lead-out interconnection layer, an area of parts of the lower shield layer and the lower electrode lead-out interconnection layer, which are opposed to each other, and an area of parts of the upper shield layer and the upper electrode lead-out interconnection layer, which are opposed to each other being respectively set so that a parasitic capacity between the lower shield layer and the lower electrode lead-out interconnection layer and a parasitic capacity between the upper shield layer and the upper electrode lead-out interconnection layer being substantially equal to each other.
According to farther another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the step of forming above a semiconductor substrate a capacitor element including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film, the method comprising the steps of: forming a lower shield layer with a plurality of holes formed in, and forming a lower electrode lead-out interconnection layer with a plurality of holes formed in, before the step of forming the capacitor element.
According to farther another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the step of forming above a semiconductor substrate a capacitor element including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film, the method comprising the steps of: forming an upper electrode lead-out interconnection layer with a plurality of holes formed in and forming an upper shield layer with a plurality of holes formed in, after the step of forming the capacitor element.
According to farther another aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the step of forming above a semiconductor substrate a capacitor element including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film, the method comprising: the steps of forming a lower shield layer with plurality of holes formed in and forming a lower electrode lead-out interconnection layer with a plurality of holes formed in, before the step of forming the capacitor element, and the steps of forming an upper electrode lead-out interconnection layer with a plurality of holes formed in and forming an upper shield layer with a plurality of holes formed in, after the step of forming the capacitor element.
As described above, according to the present invention, the shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.
According to the present invention, the lower shield layer, the lower electrode lead-out interconnection layer, the lower electrode lining interconnection layer, the upper electrode lead-out interconnection layer and the upper shield layer are all meshed, which can prevent combination of noises with the MIM capacitor while the required design rules being satisfied.
According to the present invention, the mesh-pattern of the lower shield layer and the mesh-pattern of the lower electrode lead-out interconnection layer are offset from each other in their relative positional relationship, whereby a parasitic capacity between the lower shield layer and the lower electrode lead-out interconnection layer can be made very small. According to the present invention, the mesh-pattern of the upper electrode lead-out interconnection layer and the mesh-pattern of the upper shield layer are offset from each other in their relative positional relationship, whereby a parasitic capacity between the upper electrode lead-out interconnection layer and the upper shield layer can be made very small. Thus, according to the present invention, a parasitic capacity is prohibited from affecting electric characteristics.
According to the present invention, the insulation film is formed in a height substantially equal to the upper surface of the MIM capacitor around the MIM capacitor, whereby the surface of the inter-layer insulation film is prevented from rising above the MIM capacitor, and the surface of the inter-layer insulation film can be generally at a uniform height. Accordingly, the surface of the inter-layer insulation film can be planarized by CMP, and the upper electrode lead-out interconnection layers can be buried in the inter-layer insulation films, etc. by damascene method. Accordingly, in the present invention, Cu, etc. can be used as materials of the upper electrode lead-out interconnection layers, etc.
According to the present invention, the upper electrode lead-out interconnection layer can be buried in the inter-layer insulation film having the surface planarized, whereby the upper electrode lead-out interconnection layer is prevented from breaking, etc., and high reliability can be obtained.
According to the present invention, the inter-layer insulation film, etc. can be formed on the MIM capacitor, whereby the MIM capacitor can be formed without being limited to a vicinity of the uppermost layer.
According to the present invention, the MIM capacitor can be formed without being limited to a vicinity of the uppermost layer, which allows the upper shield layer, etc. to be formed above the MIM capacitor and the upper electrode lead-out interconnection layer.
According to the present invention, the insulation film formed around the MIM capacitor and having a height substantially equal to the upper surface of the MIM capacitor functions also as a hard mask for preventing the base from being etched in patterning the layer film to form the MIM capacitor. Thus, according to the present invention, the inter-layer insulation film having the surface at a substantially uniform height can be formed without adding any step.
According to the present invention, the upper electrode of the MIM capacitor is formed thick, whereby even when the contact holes are deep down to the interconnection layer, the contact holes are prevented from passing through the upper electrode of the MIM capacitor down to the capacitor insulation film.
According to the present invention, the etching stopper film formed on the MIM capacitor can prevent the contact holes passing through the upper electrode of the MIM capacitor down to the capacitor insulation film.
According to the present invention, a plurality of the basic blocks are suitably arranged to form the patterns of the MIM capacitor, the lead-out interconnection layers, the shield layers, etc., whereby the patterns of the MIM capacitor, the lead-out interconnection layers, the shield layers, etc can be easily form by CAD or other means.
According to the present invention, based on the arrangements of the basic blocks, capacitances C1, C2, C3, and numbers n1, n2, n3 of the arranged respective basic blocks, a capacitance C of the MIM capacitor can be easily computed, which facilitates the design.
According to the present invention, the shield layers are formed larger than size of the MIM capacitor, whereby combination of noises with the MIM capacitor can be better prevented.
According to the present invention, even in a case that a gap dL between the lower shield layer and the lower electrode lead-out interconnection layer is different from a gap dU between the upper electrode lead-out interconnection layer and the upper shield layer, a width wSL of the lower shield layer is made different from a width wSU of the upper shield layer, whereby a parasitic capacity CL between the lower shield layer and the lower electrode lead-out interconnection layer can be set to be substantially equal to a parasitic capacity CU between the upper electrode lead-out interconnection layer and the upper shield layer. According to the present invention, a parasitic capacity CL between the lower shield layer and the lower electrode lead-out interconnection layer and a parasitic capacity CU between the upper electrode lead-out interconnection layer and the upper shield layer can be made substantially equal to each other, whereby noises can be more effectively shielded.
According to the present invention, not only a width wSL of the mesh-pattern of the lower shield layer but also a width wOL of the mesh-pattern of the lower electrode lead-out interconnection layer is set to be small, and not only a width wSU of the mesh-pattern of the upper shield layer but also a width wOU of the mesh-pattern of the upper electrode lead-out interconnection layer is set to be large, but a parasitic capacity CL between the lower shield layer and the lower shield layer and a parasitic capacity CU between the upper electrode lead-out interconnection layer and the upper shield layer can be set to be substantially equal to each other.
According to the present invention, the layer film remaining on the side wall of the insulation film is to be connected to a fixed potential through the vias, the conducting layers, the lower shield layer, the upper shield layer, etc., whereby variation of a dielectric capacity of the MIM capacitor can be prevented.
According to the present invention, the interconnection layers, the semiconductor elements, etc. can be disposed above and below the MIM capacitor, whereby space savings can be attained, and a chip area can be small. According to the present invention, the semiconductor device including an MIM capacitor can be inexpensively provided.